The trend towards the development of ever more highly integrated, large capacity integrated circuit memory devices has generally led to a reduction of the spacing between adjacent bit lines in such devices. This reduction in spacing can cause increased coupling capacitance between adjacent bit-lines, and thus can increase crosstalk.
FIG. 1 is a circuit diagram illustrating a twisted bit-line structure for a conventional memory device. A memory block 100 includes a plurality of sense amplifiers 121-126, a plurality of bit-line pairs (BL0, BL0)-(BL5, BL5), a plurality of wordlines WL0-WLn, and a memory cell array 141 including a plurality of memory cells M. The sense amplifiers 121-126 are positioned on both sides of the memory cell array 141. The bit-line pairs (BL0, BL0)-(BL5, BL5) are connected to respective ones of the sense amplifiers 121-126. Each bit line pair (BL0, BL0)-(BL5, BL5) includes a complementary set of bit lines, with each pair twisted near a central portion of the array 141. The wordlines WL0-WLn cross the bit-line pairs (BL0, BL0)-(BL5, BL5) at right angles, and are insulated therefrom. The memory cells M are formed at selected locations at which wordlines WL0-WLn and bit-lines (BL0, BL0)-(BL5, BL5) cross.
When a cell 101 is selected, coupling capacitance affecting the cell 101 includes coupling capacitance associated with a bit line BL2 connected to the cell 101 and coupling capacitance associated with a complementary bit line BL2 connected to the cell 101. The coupling capacitances of the complementary bit line BL2 present when the cell 101 is sensed by the sense amplifier 123 include 1/2Cbb1 and 1/2Cbb2 due to the bit line BL2 of a cell 101, 1/2Cbb3 due to the bit line BL1 of a cell 103, and 1/2Cbb4 due to the complementary bit line BL3 0 of a cell 105. The total coupling capacitance Cbbt of the bit line BL2 of the cell 101 may be expressed as: ##EQU1## Because the coupling capacitances Cbb1, Cbb2, Cbb3 and Cbb4 typically are each approximately equal to a nominal coupling capacitance Cbb, the total coupling capacitance Cbbt may be expressed as: EQU Cbbt=2Cbb. (2)
An alternative to the above-described structure is described in U.S. Pat. No. 5,144,583. This patent describes a memory architecture in which three bit lines are twisted together, with the twisted portions of the bit lines composed of different conductive materials than the straight portions. This architecture can provide improved coupling capacitance over other bit line structures. However, there is a continuing need for bit line structures that offer increased potential integration density without incurring unacceptable coupling capacitance between adjacent bit lines.